The subject invention relates to a new and improved video computing system having an automatically refreshed memory. More particularly, a video computing system is disclosed having a dynamic random access memory which is automatically refreshed without the benefit of separate refresh circuitry. In addition, the system is arranged such that the normal operation of the central processing unit need not be interrupted to carry out the refresh sequence.
In prior art computers, a variety of memory means were developed to store information. Typically, memories consist of a plurality of interconnected semiconducter devices each capable of storing a charge representing a bit of information Certain types of memories, called static memories, are capable of holding these charges for an indefinite period. Static memories however, consume a high level of power, are relatively slow, and are expensive to manufacture.
Accordingly, in the prior art, dynamic memories were developed which require less power and are relatively faster in operation. Information, stored in the form of electrical charges, may be randomly accessed from the memory. Unlike a static memory, however, the electrical charges in a conventional random access memory (RAM) decay over a period of time and eventually become unreadable. Stated differently, when the voltage level of a charge held in the memory decays below a certain threshold, it can no longer be distinguished from the off or null state. The decay rates of RAM's vary but are typically in the millisecond range. To prevent the charges in the RAM's from decaying to an unreadable level, refresh circuitry must be provided. More particularly, in the prior art, various refresh circuits were developed to maintain charges on the dynamic RAM's.
Memory locations can be refreshed by a normal read process In a typical dynamic RAM, the memory locations are arranged in a matrix configuration of columns and rows such that each position in the memory is defined by a unique column and row address. Matrix memories are generally designed such that the reading of any particular location will function to refresh all the locations in either the particular row or column which was selected. Thus, an entire matrix memory can be refreshed by reading either all the rows or columns. Accordingly, in the prior art, refresh circuits were developed which insure that all the columns or rows of the memory are read within the decay period.
During a refresh operation, direct access to the memory, by the central processing unit (CPU), must be prevented. Thus, at the beginning of each refresh cycle, a computer interrupt signal is generated preventing the CPU from accessing the memory until the refresh operation is complete. The necessity of refreshing dynamic memories therefore results in a significant reduction in computer processing speed since the access to memory by the CPU must be continuously interrupted.
In order to reduce this loss of computing speed, a variety of intelligent refresh circuits have been developed. For example, U.S. Pat. No. 3,737,879 issued June 5, 1973 to Greene, et al. discloses an intelligent refresh circuit having a memory matrix. In the latter circuitry, the condition of the memory is monitored and the refresh operation is carried out only when necessary. By this arrangement, the percentage of time which the CPU is denied access to the memory is reduced.
Another example of intelligent refresh circuitry is disclosed in U.S. Pat. No. 4,112,513, issued Sept. 5, 1978 to Elsner. In the latter patent, a system is disclosed which selectively refreshes particular sections of the memory, permitting CPU access to the remainder of the memory. However, as can be appreciated, the latter prior art systems still deny full access to the memory. Further the prior art systems require fairly complex circuitry. Accordingly, it would be desirable to provide a new and improved computing system which does not require the interruption of the central processing unit and eliminates the use of refresh circuitry thereby reducing the cost and complexity of the system.
Many computing systems now utilize a cathode ray tube (CRT) as an input/output device. A variety of CRT's have been developed for various uses. For example, vector oscilloscopes, having a high persistence phosphor, are suitable for some systems However, more frequently, raster scanning oscilloscopes are used due to their low cost and high reliability. Raster scan oscilloscopes are well known in the art and need not be described in detail. Briefly, a raster scan oscilloscope includes a cathode ray tube which emits a beam of electrons onto a phosphor coated screen having a low persistance. Shifting magnetic fields cause the electron beam to sweep across the phosphor coated screen in regular horizontal lines. At the end of a full screen sweep, the electron beam is returned to its starting point to begin sweeping again. Since the phosphor coating has a low persistence, the beam must continually sweep the screen to maintain the visual image.
The information to be displayed on the video screen is typically contained in the system memory. One method of storing and displaying the video information is to divide each horizontal scan line into a number of individual points or pixels. Each pixel can be represented by one location in the computer memory. This arrangement is frequently called a bit map. Data stored in memory is transfered to the CRT and used to modulate the electron beam to produce the video image.
In most prior art raster scan systems, a controller is provided which sequentially generates addresses corresponding to the locations in the computer memory where the video information is stored. The controller must have priority access to the memory to obtain the video information stored therein for refreshing the image on the CRT. Accordingly, prior art systems are designed such that when information is required, an interrupt signal is generated preventing the CPU from accessing any data in the memory. During the interrupt period, the controller is permitted direct memory access to the information contained in the dynamic memory. Typically, the information is read out of memory a line at a time and output on the video screen. As can be appreciated, the interrupting of the CPU to obtain video information results in loss of computing speed and power. Thus, it would be desirable to provide a new and improved system where computing speed is not sacrificed by the need for direct memory access by the video system.